Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
FIG. 1 shows a cross-section of a typical prior art NROM array. The array is comprised of a silicon substrate 100 with a gate oxide layer 101 formed over the substrate 100. A silicon nitride layer 102 is formed over the gate oxide 101. Each transistor 140-142 is comprised of two charge storage regions 110 and 111 in the nitride layer 102. An intergate insulator 107 is formed over the nitride layer 102 prior to forming the control gate/wordline 120-122 of each transistor 140-142 over the intergate insulator 107 and substantially between the source/drain regions 130-133.
The minimum feature size of the transistors 140-142 of FIG. 1 is described by F. The density is therefore one bit for each 4F2 units surface area. This is typically described as a density of 4F2/bit.
As computers become smaller and their performance increase, the computer components should also go through a corresponding size reduction and performance increase. To accomplish this, the transistors can be reduced in size. This has the effect of increased speed and memory density with decreased power requirements.
However, a problem with decreased flash memory size is that flash memory cell technologies have some scaling limitations due to the high voltage requirements for program and erase operations. As MOSFETs are scaled to deep sub-micron dimensions, it becomes more difficult to maintain an acceptable aspect ratio. Not only is the gate oxide thickness scaled to less than 10 nm as the channel length becomes sub-micron but the depletion region width and junction depth must be scaled to smaller dimensions.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device having increased memory density and performance.